1. Field of the Disclosure
The present disclosure relates to an aqueous slurry for use in chemical mechanical polishing (CMP) of semiconductor substrates. More particularly, the present disclosure relates to an aqueous slurry that is particularly useful for polishing multiple substrates present in complex advanced node structures such as, but not limited to, tetra-ethyl ortho-silicate (TEOS) or similar, interlayer dielectrics, silicon nitride (SixNy), silicon carbide (SiC), polysilicon, high k materials, metals, alloys, and co-formed materials thereof.
2. Description of the Related Art
In the semiconductor industry there is a continual drive to reduce the size of integrated circuits, in order to increase the density of active components. In order to achieve higher component density, current research is directed towards utilizing innovative substrate materials and planarization schemes. The problem that arises is that present polishing compositions are incapable of achieving the planarity requirements critical for maximal circuit performance.
As described in U.S. Pat. No. 7,166,506, to Prince et al. and shown in FIG. 1, in the formation of a transistor, an interlayer dielectric is deposited over the device structure, which has a polysilicon gate. This dielectric layer is planarized via CMP until the polysilicon gate is exposed. In the process of FIG. 1, the polysilicon gate is exposed by adequate CMP removal of the dielectric layer, etch stop layer, hardmask, and part of the spacers. In conventional integration schemes, a two step process is required. A CMP composition such as that disclosed in U.S. Pat. Nos. 5,759,917 and 6,027,554 could be used to remove the dielectric layer, but it would have minimal impact on the etch stop layer. A second composition as described in U.S. Pat. Nos. 6,984,588 and 7,217,989 would then be utilized to remove the etch stop layer. Furthermore, should the device structure displayed in FIG. 1 follow a metal gate integration scheme, the polysilicon gate would be removed and replaced by a metal gate such as aluminum. The aluminum deposition would require yet another planarization step, and a third composition.
U.S. Pat. No. 6,255,211 relates to silicon carbide (SiC) integration schemes. FIG. 2 shows a typical scheme associated with 3D system level integration where multiple layers are interconnected using through-silicon-vias (TSV). In the case of 3D system level devices, a very thin layer of SiC serves as a stop layer in the back end of the line (BEOL) processes. While common CMP chemistries (such as those disclosed in U.S. Pat. No. 6,255,211) can achieve relatively high silica to silicon carbide (50:1) selectivity, and can be utilized for SiC barrier schemes, they are not readily applicable to 3D system level device integration, because the SiC polish rate is relatively high, regardless of the selectivity value.
Thus, there is a need for a CMP slurry for enabling the use of innovative substrate materials and planarization schemes, and to enhance the capability of current and previous integration schemes to improve FEOL and/or BEOL CMP. Current slurries are only useful for particular applications, requiring the use of many different kinds of slurries, which adds significantly to the cost of the related processes, because requires users to stock many different slurries.